The present invention relates to a semiconductor device that uses a silicon carbide semiconductor substrate and a method for fabricating the device, and more particularly relates to a silicon carbide semiconductor power device handling high currents and voltages and a method for fabricating the device.
A power device is expected to be capable of handling high currents and voltages and low power loss. Although a power device that uses silicon (Si) semiconductor has conventionally been predominant, a power device that uses silicon carbide (SiC) semiconductor is recently getting attention and being developed. Since the dielectric breakdown field of silicon carbide semiconductor is ten times greater than that of silicon, the device that uses silicon carbide semiconductor has high reverse blocking voltage even if a depletion layer at a pn junction or a Schottky junction is thinned. Therefore, the thickness of the resulting device can be reduced, and dopant concentration can be increased. Accordingly, silicon carbide is highly expected as a material for a power device that has high reverse blocking voltage and a low power loss.
FIG. 9 is a cross-sectional view illustrating, as an example of a conventional silicon carbide semiconductor device, the structure of a double implantation MOSFET. Herein, the “double implantation MOSFET” refers to the MOSFET that is formed by using a double implantation process. As shown in FIG. 9, in the conventional silicon carbide semiconductor device, on a low-resistance substrate 101 made of silicon carbide, a high resistance layer 102 having a resistance higher than that of the substrate 101 is epitaxially grown. In a surface region of the high resistance layer 102, p-type well regions 103 are formed by selective ion implantation. By ion implantations, each p-type well region 103 is provided at the inside thereof with: a n-type source region 105 having a high concentration; and a p-type p+ contact region 104 surrounded by the source region 105 adjacent thereto.
A gate insulating film 106, formed of a thermal oxide film, is formed on a portion of the high resistance layer 102 sandwiched between the two well regions 103 and on ends of the source regions 105 within the two well regions 103. On the gate insulating film 106, a gate electrode 109 is formed. On each p+ contact region 104 and on an end of the source region 105 located to laterally surround the p+ contact region 104, a source electrode 108 is provided so as to be in ohmic contact with the associated contact region 104. Furthermore, on the entire back side of the substrate 101, a drain electrode 107 is provided so as to be in ohmic contact with the substrate 101.
Over the high resistance layer 102, the p-type well regions 103, the p+ contact regions 104 and the source regions 105, an interlayer dielectric film 110 is deposited. The interlayer dielectric film 110 is provided with contact holes that reach the source electrodes 108 and a contact hole that reaches the gate electrode 109. On the interlayer dielectric film 110, interconnects 111 and 112, each made of aluminum and having a thickness of 2 μm, are provided so as to fill the contact holes. The interconnects 111 are located on the source electrodes 108, and the interconnect 112 is located on the gate electrode 109. The above-described structure is disclosed, for example, in prior art document 1 (Japanese Unexamined Patent Publication No. 11-297712).
As the source electrodes 108, nickel, nickel silicide or a mixture thereof is normally used. This is because nickel or nickel silicide has the property of being easily in ohmic contact with n-type silicon carbide. As another example of this structure, prior art document 2 (Toshiyuki Ohno, “Current State of Process Technology of Forming Element using SiC”, The Transaction of The Institute of Electronics, Information and Communication Engineers, Vol.J81-C-II, No.1, pp. 128–133, January 1998) discloses a method in which nickel is used as the source electrodes or drain electrode of an n-type silicon carbide semiconductor device and an annealing is performed at a temperature of 900° C. or more in an atmosphere of an inert gas such as argon or nitrogen, thus obtaining an ohmic characteristic. As the interlayer dielectric film 110, a silicon oxide film with a thickness of about 1 μm is normally used. This is because the breakdown electric field of silicon oxide is high, and a silicon oxide film can easily be formed by a CVD process or the like.
However, in the semiconductor device with the above-described structure, when the interlayer dielectric film 110 has been deposited, the adhesion between nickel constituting the source electrodes 108 and silicon oxide constituting the interlayer dielectric film 110 is poor, which causes the problem that the silicon oxide on the source electrodes 108 undesirably peels off. In order to solve such a problem, prior art document 3 (Japanese Unexamined Patent Publication No. 2002-093742), for example, discloses a method in which a resist mask is formed over silicon oxide, and sidewalls etching is carried out in the step of performing etching for forming a via hole in an interlayer dielectric film, thus forming the via hole having a width larger than that of an opening in the resist mask. Thereafter, nickel is deposited and lifted off using the same resist mask, thus providing a gap between the sidewalls of the via hole and the nickel film.
Prior art document 4 (Japanese Unexamined Patent Publication No. 10-125620) discloses a method for preventing a nickel interconnect from peeling off by providing a barrier metal between silicon oxide and the nickel interconnect.
However, in the method for providing a gap between the via hole and source electrode, water is likely to be absorbed into this gap, and there occurs the problem of a reduction in mechanical strength. On the other hand, in the method for providing a barrier metal, an annealing for forming an ohmic contact between the nickel electrode and substrate is performed at a temperature of about 1000° C. after an interlayer dielectric film has been formed, and therefore, there occurs the problem that the nickel in contact with the interlayer dielectric film within a contact hole undesirably reacts with the interlayer dielectric film, thus reducing the reliability of the resulting device.